c-Si cell technology roadmap

To keep reducing dollar-per-watt price of panels, manufacturers are actively seeking innovative technologies to be implemented into existing production lines. The areas can be improved include raw material cost, cell structure optimization, module assembly and installation cost reduction etc. This topic is mainly focused on cell structure optimization. Basic ideas are targeted at adding back-side passivation, enabling lightly-doped front-emitter, maximizing front side light exposure and collection, and increasing emitter area. Figure 1 shows the general trend of cell efficiency development from AMAT.

Fig 1 c-Si Cell Technology Roadmap (Courtesy of Applied Materials)

The following are some brief discussion about the ways for further improvement of cell performance and/or reduction of manufacturing cost.

(1) Adding rear-side passivation. Conventional cell has only front-side PECVD SiNx passivation, which is typically useful for n-emitter because the fixed positive charges induced on this thin layer (e.g. <10nm) repel the minority carriers-holes and reduce the chance of surface recombination. However, the passivation of p-type back side is more effective with Al2O3 because of fixed negative charges [1], which is usually deposited by ALD and has throughput issue. The rear-side passivation is also coupled with localized back surface field to further utilize the long-wave length light better. 

(2) Enabling lightly-doped front emitter. The same high doping concentration on the entire front surface by POCl3 diffusion is formed for conventional cell to achieve good ohmic contact between metal and wafer substrate for reduction of series sheet resistance. This situation causes unnecessary heavy doping profile for non-metal area-the emitter, which in turn increases charge recombination rate due to Auger effect. To avoid this situation, a so-called Selective Emitter structure can be considered. The structure has low sheet resistance (e.g. <45 Ω/sq) under metallization areas and higher sheet resistance (e.g. >100 Ω/sq) areas for emitter. Thus, the minority charge carriers generated close to the surface by short wavelengh light, which has weak penetration capability, can have less chance to undergo annihilation. In other words, selective emitter increases IQE at short wavelength so that it improves overall cell performance.

(3) Maximizing front side light exposure and collection. This effort mainly involves back-contact structures, high-aspect-ratio (HAR) metallization and front surface texturing. Back contact includes Interdigitated Back Contact (IBC), Metal Wrap Through (MWT), and Emitter Wrap Through (EWT). HAR metallization is applied to narrow the metal width by increasing line height so that conductivity is not compromised, for examples, AMAT's Double Printing and DEK's PoP methods. Front surface texturing is being further improved to include invert pyramid structure and laser patterned honey cone etc.

(4) Increasing emitter area. This work has purposes of reducing metal contact area on wafer and giving more room for emitter so that more minority charge carrier can be generated and utilized from emitter. Point contact of metallization method is an example.

References
[1] Jan Schmidt et al. "Atomic-layer-deposited of aluminum oxide for the surface passivation of high efficiency Si solar cells", 33th IEEE PVSC (2008), pp.??